1. Field of the Invention
The present invention relates to systems and methods for implementing phase lock loop (PLL) circuits in multimode radios, and particularly for implementing PLL circuits in multimode code division multiple access (CDMA) cellular radios that include global positioning system (GPS) receivers and other global systems for mobile communications (GSM) technologies.
2. Description of the Related Art
Phase Locked Loop (PLL) circuits are well known and used for frequency control in a variety of applications. For example, they can be configured as frequency multipliers, demodulators, tracking generators or clock recovery circuits. Each of these applications may demand different characteristics, however they all use the same basic circuit concept.
FIG. 1A illustrates a block diagram of a conventional PLL circuit 100. The operation of this circuit 100 is typical of all phase locked loops. It is basically a feedback control system that controls the phase of a voltage controlled oscillator (VCO) 108. The reference input signal 102 is applied to one input of a phase comparator 104. The other input of the phase comparator 104 is connected to the output of the VCO 108 via the feedback loop 110. The output of the phase comparator 104 is a voltage proportional to the phase difference between the two inputs. This signal is applied to the loop filter 106. The characteristics of the loop filter 106 can be selected to achieve the desired closed loop dynamic characteristics of the PLL circuit 100. The filtered signal controls the VCO 108 and the output of the VCO 108 is directed back to the phase comparator 104 via the feedback loop 110 to xe2x80x9clockxe2x80x9d the output to the reference input signal 102.
Normally the loop filter 106 is designed to match the characteristics required by the application of the PLL circuit 100. If the PLL circuit 100 is to acquire and track a varying reference signal 102, the bandwidth of the loop filter 106 will be greater than if it is applied to a more limited input frequency. The frequency range which the PLL circuit 100 will accept and lock on is known as the capture range. Once the PLL circuit 100 is locked and tracking a signal, the range of frequencies that the PLL circuit 100 will follow is called the tracking range. Generally, the tracking range is larger than the capture range.
The characteristics of the loop filter 106 also determine how quickly the frequency of the reference signal 102 can change and still maintain lock. This is termed as the maximum slewing rate. The narrower the loop filter 106 bandwidth is, the slower the response and smaller the capture range will be.
PLL circuits are particularly useful in communications electronics for generating accurate and stable oscillator reference signals in radio receivers and transmitters. For example, the PLL circuit output can be used for channel selection for such receivers and transmitters.
However, evolving and diversifying communications standards and particularly those related to cellular radios, have resulted in a need for radio transceivers which can operate in different modes and accommodate more than one standard and frequency band. For example, a cellular radio which supports CDMA 1xc3x97 and/or global system for mobile communications (GSM) general packet radio service (GPRS) and wideband code division multiple access (WCDMA) is desirable. To support multimode capabilities, there is a need for more than one reference oscillator within a single transceiver. A conventional design would include two separate PLL circuits and switch between them as necessary, however such an approach increases the size, cost and overall design efficiency of the transceiver. In addition, there is also a need for such PLL circuits to quickly acquire the new frequency when they are switched from one band to another.
Accordingly, there is a need in the art for PLL circuits which operate across multiple frequencies to support one or more VCOs and multiple standards in multimode radio cellular devices. For example, standards such as CDMA 1xc3x97, GPS and/or GSM/GPRS and WCDMA should all be supportable by such circuits. There is also a need for such circuits to operate at very high speed, quickly acquiring a new frequency when they are switched to a different mode. Moreover, there is a need in the art to obtain all of the foregoing, while maximizing the design efficiency and minimizing size and costs. The present invention meets all these needs.
An apparatus and method for filtering a signal in a phase lock loop is disclosed. An typical apparatus for filtering a phase error signal comprises a first filter subcircuit receiving a phase error signal from a phase comparator and filtering the error signal when enabled, a second filter subcircuit receiving the phase error signal from the phase comparator and filtering the error signal when enabled and first and second enable switches which are activated in combination to control filtering of the error signal. The first filter subcircuit is enabled by activating a first combination of the enable switches and the second filter subcircuit is enabled by activating a second combination of the enable switches. A fast acquisition (FAQ) subcircuit can also be used to temporarily underdampen the filter and improve overall performance of the phase lock loop circuit. The filter can be used to obtain multimode operation in a cellular radio.
In one embodiment, where the second filter subcircuit has a higher bandwidth than the first filter subcircuit, the second filter subcircuit can be momentarily activated to fast acquisition with the first filter subcircuit.
In another embodiment, the first filter subcircuit and the second filter subcircuit share common circuit elements. In addition, when the first enable switch is activated, either filter subcircuit can be alternately referenced to a ground or a common cathode voltage selectable by a reference switch. Futhermore, the first and second enable switches can be field effect transistors. The filter can be used to obtain multimode operation in a cellular radio.
In one embodiment, a fast acquisition subcircuit including a fast acquisition enable switch and wherein fast acquisition of one of the first and second filter subcircuits is enabled when the fast acquisition switch is enabled. The fast acquisition subcircuit can be temporarily enabled to underdampen the filter, thereby improving the overall performance of the PLL circuit. The fast acquisition subcircuit can comprise a fast acquisition resistor which is used to alter the resistance characteristic of the filter subcircuit when the fast acquisition switch is enabled. Furthermore, the fast acquisition subcircuit can be coupled to the first or second filter subcircuit. As with the filter subcircuits, the fast acquisition subcircuit can be alternately referenced to a ground and common cathode voltage selectable by a reference switch.
In another shared element embodiment of the invention, the shared common circuit elements are a first capacitor and a first resistor in series both connected in parallel to a second capacitor. Furthermore, the first filter subcircuit can be a subset of the second filter subcircuit.
In different embodiments of the invention various switch combinations may be used to operate the filter and change its characteristics. In one embodiment the first combination comprises activating the first enable switch and deactivating the second enable switch which places a first capacitor in series connection with a first resistor both in parallel connection with second capacitor. The second combination comprises deactivating the first enable switch and activating the second enable switch which places a first and third capacitor in parallel connection, both in series connection with a first resistor and the first and third capacitor and first resistor are all placed in parallel connection with a second and fourth capacitor in series connection. In another embodiment, the first combination comprises activating the both the first enable switch and the second enable switch which places a first capacitor in series connection with a first resistor both in parallel connection with second capacitor. The second combination comprises deactivating both the first enable switch and the second enable switch which places a first and third capacitor and a first resistor all in series connection, all placed in parallel connection with a second and fourth capacitor in series connection.
In another embodiment, the first and second filter subcircuits each comprise a resistor-capacitor filter including a first capacitor and a first resistor in series both connected in parallel to a second capacitor.
Finally, the first and second filter subcircuits of the present invention can be implemented on a single integrated circuit. The first and second enable switches can be internal or external to the integrated circuit.
In addition the present invention also teaches a method having features like those of the described apparatus. The typical method comprises the steps of filtering a signal in a phase lock loop, comprising the steps of receiving a phase error signal from a phase comparator, filtering the error signal with a first filter subcircuit when a first enable switch is activated and filtering the error signal with a second filter subcircuit when a second enable switch is activated.